1. Technical Field
The disclosure concerns methods of passivating, cleaning or reducing oxides from semiconductor surfaces.
2. Background Discussion
Wet cleaning is a semiconductor process for cleaning or functionalizing the semiconductor surface prior to process operations involving gate dielectric deposition or contact formation, for example. In wet cleaning, wafers to be cleaned are submerged in a bath of a cleaning agent, such an aqueous solution of HF, for example. As semiconductor structures are changing to include 3-dimensional (3D) shapes such as finFET devices with ever-increasing aspect ratios, wet cleaning will create more problems. The term finFET refers to a field effect transistor (FET) formed on a semiconductor structure shaped as a thin wall (or fin) of semiconductor material. The fin serves as a 3-dimensional structure, in which are formed source and drain regions and a channel between them, all formed as adjacent 3-dimensional sections of the fin. A gate overlies the channel on three sides of the wall. The complete structure is a field effect transistor (FET) and is referred to as a finFET.
One of the main problems with wet cleaning is that it will cause collapse of the device (e.g., the fin structure) at higher aspect ratios.
In the cleaning of high aspect ratio structures such as those involved in finFET devices, the deformation caused by surface tension and capillary forces involved in wet cleaning can cause collapse of the device (e.g., the fin). The scaling roadmap of these devices requires further reduction in the device width L and inter-device distance d, while the feature height H is expected to increase, which will further aggravate the problems associated with pattern collapse. The structural deformation depends inversely on d and L3 and is proportional to H4. Theoretical modeling indicates that pattern collapse due to wet cleaning will start to become a significant problem at the aspect ratios and dimensions required for 10 nm node devices sizes.
Another problem associated with wet cleaning is that of substrate (workpiece) consumption, which was not a concern for planar devices. However, for 3D devices (such as finFET structures), even 1 nm of substrate consumption on both sides of the device (or fin) can lead to 25% reduction in the fin width, for an 8 nm wide fin. To avoid these issues, an alternative to wet cleaning is needed.
One more challenge in cleaning of Ge and group III-V compound semiconductor surfaces is the high surface reactivity of these materials. Ge—Ge and group III-V compound bonds have lower bond enthaplies as compared to silicon, as shown below in Table 1.
TABLE 1BondEnergy (eV)Ge—Ge2.63Ge—O 6.59Ge—H 3.21Si—Si3.28Si—H 2.99 In—As2.01Ga—As2.09
Traditional plasma sources such as inductively coupled sources and capacitively coupled sources have plasma ion energy ranges above the bond energies of many of the materials of Table 1 and are known to cause significant surface damage on some materials listed in the table, particularly the materials having bonding energies below the Si—Si bonding energy, such as those found in group III-V compound semiconductor elements. Dangling Ge and group III/V element bonds on the surface are the root cause of high density of interface states and Fermi level pinning which is detrimental for transistor performance.